A 4mask (i.e., four-time mask patterning) process currently adopted for manufacturing an array substrate includes: a Gate Mask process (i.e., a mask patterning process for gate electrodes and gate lines of the array substrate), an SDT Mask process (i.e., a mask patterning process for an active layer of the array substrate as well as source electrodes, drain electrodes and data lines located on the active layer), a PVX Mask process (i.e., a mask patterning process for via holes of the array substrate), and an ITO Mask process (i.e., a mask patterning process for pixel electrodes of the array substrate).
A mask plate which is currently adopted in the SDT Mask process is a half tone mask plate. A specific structure of a current half tone mask plate is generally shown in FIG. 1. The half tone mask plate 00 includes a totally light shielding region a, a semi-transparent region b and a totally light transmitting region c. When the half tone mask plate is used to form an active layer as well as source electrodes, drain electrodes and data lines located on the active layer by performing one time SDT Mask process on a semiconductor layer and a metal layer which are sequentially stacked, the totally light shielding region of the half tone mask plate corresponds to a source electrode region, a drain electrode region and a data line region; the semi-transparent region of the half tone mask plate corresponds to a region of the active layer located between the source electrode region and the drain electrode region; and a region of the metal layer except for regions of the metal layer which correspond to the totally light shielding region and the semi-transparent region of the half tone mask plate corresponds to the totally light transmitting region of the half tone mask plate, so as to respectively etch the semiconductor layer and the metal layer in the totally light transmitting region of the half tone mask plate as well as the metal layer in the semi-transparent region of the half tone mask plate, and remain the semiconductor layer and the metal layer in the totally light shielding region of the half tone mask plate to form the active layer, the source electrodes, the drain electrodes and the data lines.
As shown in FIG. 1, after using the half tone mask plate 00 to expose (i.e., light 400 passes through the half tone mask plate 00 and irradiate on photoresist) and develop photoresist on the metal layer 300, some photoresist 100b is remained on the metal layer 30 in the semi-transparent region b of the half tone mask plate 00. Thus, before etching the metal layer in the semi-transparent region of the half tone mask plate, it is needed to remove the photoresist remained on the metal layer in the semi-transparent region of the half tone mask plate through an ashing process in advance. Since a dry etching equipment has a function of ashing and removing the photoresist, thus, at present, in order to simplify the processes, a dry etching method is generally used to etch the metal layer in the semi-transparent region of the half tone mask plate. However, since some materials which are not easily volatile and not inconvenient to be removed can be produced in the dry etching process, thus, a partial concentration of etching plasma is affected, resulting in poor uniformity of the etching. This can easily lead to occurrence of problems that the metal layer in the semi-transparent region of the half tone mask plate is remained or over-etched, resulting in that manufactured thin film transistors (TFT) of the array substrate have poor performance and then the final manufactured array substrate has poor quality.
From the above, as present, when the dry etching method is used to etch the metal layer in the semi-transparent region of the half tone mask plate, since the uniformity of the etching is poor, thus the manufactured TFT have poor performance and then the final manufactured array substrate has poor quality.